Pilot line(s) for 2D materials-based devices (RIA)
TOPIC ID: HORIZON-CL4-2024-DIGITAL-EMERGING-01-31
Type of Action:
HORIZON-RIA HORIZON Research and Innovation Actions
Type of MGA:
HORIZON Action Grant Budget-Based [HORIZON-AG]
Deadline model:
Single-Stage
Planned opening date:
15 November 2023
Deadline date:
19 March 2024 17:00:00 Brussels time
Expected Outcome:
Projects are expected to contribute to the following outcomes:
- Broadly accessible pilot line(s) fostering the creation of electronic and photonic devices and systems (co-)integrating two-Dimensional Materials (2DM).
- Significant progress towards the adoption of the 2DM in the silicon and semi-conductor arena by allowing the production of new (co-)integrated devices and systems in a quality controlled way.
Scope:
Proposals shall continue the efforts started in the 2D experimental Pilot Line of the Graphene Flagship and build on the IP developed therein, to establish a 2DM pilot line(s), where European companies, research centers and academic institutions, can produce on a pilot scale novel electronic and/or photonic devices and systems integrating 2DM.
Proposals should focus on the (co-)integration of 2DM with established technologies such as CMOS[1] integration and heterogeneous integration.
Proposal should include supply of standard semiconductor technologies such as CMOS, ASICs[2], planarized waveguides already adapted/optimized for 2DM co-integration.
Proposals should specify targeted added value(s) against current technologies of the integrated devices and systems. Proposals should consider the following TRLs: for Electronics applications starting TRL 3 with ending TRL 5 and for photonics applications starting TRL 3-4 and ending TRL 5-6.
Multidisciplinary research and innovation activities should address all of the following:
- Building the toolkit and design modules necessary for creating prototype devices and systems, characterise and assess their performance and their ability to cover the device requirements of the targeted applications.
- Process characterisation and monitoring to control and guarantee quality of relevant device parameters and to allow yield predictions of the integrated devices.
- Adaptation of standard semiconductor technologies including passivation schemes, strategies to align devices over different technologies, modules to contact the 2D devices with the periphery, optimized planarization strategies and packaging services.
- Reliability and packaging requirements;
- Implementing multiple wafer runs or other offering to best cover business opportunities;
- Defining a sustainable model of functioning beyond the project lifetime and include activities preparing for the later transfer of the pilot line to an industrial production environment; examples of such activities include addressing relevant cost issues and market perspectives, potential business partners, etc.
Proposals submitted under this topic should include a business case and exploitation strategy, as outlined in the introduction to this Destination.
Research should build on existing standards or contribute to standardisation. Interoperability for data sharing should be addressed.
Proposals should build on or seek collaboration with existing projects and develop synergies with other relevant European, national or regional initiatives, funding programmes and platforms. In particular projects are expected to develop synergies and relate to activities and outcomes of the projects selected under the other topics of ‘Graphene and 2D materials: Europe in the lead’ and where relevant of the KDT JU.
Proposals should also cover the contribution to the governance and overall coordination of the Graphene Flagship initiative.
In this topic the integration of the gender dimension (sex and gender analysis) in research and innovation content is not a mandatory requirement.
Specific Topic Conditions:
Activities are expected to start at TRL 3-4 and achieve TRL 5-6 by the end of the project – see General Annex B.
[1]Complementary metal–oxide–semiconductor (CMOS)
[2]Application-specific integrated circuit (ASIC)
Topic Eligibility and Documents: https://ec.europa.eu/info/funding-tenders/opportunities/docs/2021-2027/horizon/wp-call/2023-2024/wp-13-general-annexes_horizon-2023-2024_en.pdf
Kindly Apply Here: